A typical computer system includes logic circuitry that operates in response to a clock signal. In general, both the operational speed and the electrical power dissipation of the logic circuitry is directly related to a frequency of the clock signal. One way to reduce the electrical power dissipation of the logic circuitry, at the cost of reduced operational speed, is to reduce the frequency of the clock signal. One way to vary the frequency of the clock signal is to generate multiple clock signals having different frequencies, and to select between the multiple clock signals dependent on operational speed and power dissipation requirements.
Alternately, or in addition, the logic circuitry may need to operate at any one of several different clock signal frequencies. For example, the logic circuitry may be a bus interface designed to operate in accordance with the proposed PCI-X bus interface standard that specifies the ability to operate at both 66 MHz and 133 MHz. Generating a 66 MHz clock signal and a 133 MHz clock signal and selecting between them would allow the logic circuitry to operate at both 66 MHz and 133 MHz.
Circuits for selecting between multiple clock signals are generally called clock signal multiplexers or selectors. It is noted, however, that some clock signal multiplexers or selectors may produce narrow pulses or “glitches” when switching from one clock signal to another. As defined herein, a glitch or “runt” pulse is a pulse having a width that is less than a width of the highest frequency input clock signal. In general, such glitches or runt pulses may produce logic errors within the logic circuitry. In one specific example, an edge-triggered flip-flop receiving a clock signal having a glitch or runt pulse may exhibit a phenomenon known as “metastability.”
In general, edge-triggered flip-flops have required setup times and hold times. The setup time is an amount of time the input signal must be stable before a transition of the clock signal, and the hold time is an amount of time the input signal must be stable after the transition of the clock signal. When an input signal changes (i.e., leaves a defined logic region) during either the setup time or the hold time of an edge-triggered flip-flop, the operation of the flip-flop is, in general, unpredictable. More specifically, an output signal produced by the edge-triggered flip-flop may not correctly reflect the logic values of the input signals. Further, if the output signal changes, the transition may occur much more slowly than normal. This unusual behavior of edge-triggered flip-flops when setup or hold times are violated is linked to the unstable “metastable” state existing in all bistable storage elements, and is generally referred to as metastability.
The metastability problem also arises in synchronizer circuits used to synchronize asynchronous input signals to clock signals. For example, a typical personal computer (PC) includes a mouse and a keyboard for receiving user input. Input signals from the mouse and keyboard are in general asynchronous to any clock signals used to synchronize operations of the PC. Before being used in the PC, the asynchronous input signals from the mouse and keyboard are first synchronized to a clock signal of the PC.
A common synchronizer circuit for synchronizing an asynchronous input signal to a clock signal includes an edge-triggered D flip-flop (a bistable storage element) receiving the asynchronous input signal at an input terminal. In response to either a rising edge transition or a falling edge transition of the clock signal provided to a clock control terminal, the edge-triggered D flip-flop samples a logic value of the asynchronous input signal at the input terminal and produces the logic value at an output terminal. However, the metastability problem described above arises when the asynchronous input signal is generated (i.e., is undefined or leaves a defined logic region) during either the setup time or the hold time of the edge-triggered D flip-flop.
A typical approach to the metastability problem in synchronizer circuits is to add more D flip-flops in cascade until an acceptable mean time between failure (MTBF) value is achieved. Another problem arises, however, in that each edge-triggered D flip-flop added in cascade also increases an amount of time a synchronizer circuit requires to select between multiple clock signals (i.e., increases a latency of the synchronizer circuit). This increased latency is disadvantageous for high-speed systems.
It would therefore be desirable to have a clock signal selector circuit that does not produce an output clock signal having undesirable glitches or runt pulses, has a reduced probability of erroneous output due to metastability, and wherein a reduction in the probability of erroneous output due to metastability is not achieved at a cost of increased latency.